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| VRAM Austin Semiconductor, Inc. 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM AVAILABLE AS MILITARY SPECIFICATIONS * Military Processing Flow(SM Level) * -55C to 125C temperature (Top View) 64-Pin Ceramic Flatpack (HKC) SM55161A Production PIN ASSIGNMENT FEATURES * Organization: - DRAM: 262 144 by 16 Bits - SAM: 512 by 16 Bits * Dual-Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and SAM Ports * Bidirectional Data-Transfer Function From the DRAM to the Serial-Data Register, and from Serial Data Register to DRAM * (8 x 8) x 2 Block Write feature for fast area fill * Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design * Byte-Write Control (CASL, CASU) Provides Flexibility * Extended Data Output for Faster System Cycle Time * Enhanced Page-Mode Operation for Faster Access * CAS-Before-RAS (CBR) and Hidden-Refresh Modes * Long Refresh Period: Every 8 ms (Maximum) * Up to 50-MHz Uninterrupted Serial-Data Streams * 512 Selectable Serial-Register Starting Locations * SE-Controlled Register-Status QSF * Split-Register-Transfer Read for Simplified Real-Time Register Load * Programmable Split-Register Stop Point * 3-State Serial Outputs Allow Easy Multiplexing of Video-Data Streams * Pin-out Compatible upgrade from SM55161 * Compatible With JEDEC Standards PIN DESCRIPTIONS PIN A0-A8 CASL\, CASU\ DQ0-DQ15 DSF NC/GND DESCRIPTION Address inputs Column-Address Strobe/Byte Selects DRAM Data I/O, Write Mask Data Special Function Select Special-Function Select No Connect/Ground (NOTE: Not connected internally to VSS) Special-Function Output Row-Address Strobe Serial Clock Serial Enable Serial-Data Output Output Enable, Transfer Select 5V Supply (TYP) Ground DRAM Write-Enable Select OPTIONS * Timing 70ns access 75ns access 80ns access * Package 68 pin PGA 64 pin Flatpack * Operating Temperature Ranges - Military (-55oC to +125oC) - Industrial (-40oC to +85oC) MARKING -70 -75 -80 QSF RAS\ SC SE\ SQ0-SQ15 TRG\ VCC GB HKC VSS WE\ M suffix I suffix For more products and information please visit our web site at www.austinsemiconductor.com Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 1 VRAM Austin Semiconductor, Inc. PERFORMANCE RANGES DESCRIPTION Access Time Row Enable Access Time Serial Data DRAM Cycle Time DRAM Page Mode Serial Cycle Time Operating Current, Serial Port Stand-by Operating Current, Serial Port Active SYM ta(R) ta(SQ) tc(W) tc(P) tc(SC) ICC1 ICC1A 130 45 22 165 210 MIN -70 MAX 70 20 140 48 24 165 210 MIN -75 MAX 75 23 150 50 30 210 195 MIN -80 MAX 80 25 UNITS ns ns ns ns ns mA mA SM55161A Production GB PACKAGE (Bottom View) & PIN ASSIGNMENTS PIN No. J1 J2 J3 J4 J5 J6 J7 J8 J9 H1 H2 H3 H4 H5 H6 H7 H8 H9 G1 G2 G3 G4 G6 G7 G8 G9 F1 F2 F3 F7 F8 F9 E1 E2 SMJ55161A Rev. 1.6 03/05 NAME DQ1 SQ3 DQ3 DQ4 DQ5 DQ6 SQ7 CASL\ A8 DQ0 SQ2 DQ2 SQ4 SQ5 SQ6 DQ7 WE\ A7 SQ0 SQ1 VDD2 VSS2 VDD2 VSS2 RAS\ A6 TRG VSS1 VDD1 VDD1 VDD1 A5 SC VDD1 PIN No. E8 E9 D1 D2 D3 D7 D8 D9 C1 C2 C3 C4 C6 C7 C8 C9 B1 B2 B3 B4 B5 B6 B7 B8 B9 A1 A2 A3 A4 A5 A6 A7 A8 A9 NAME VSS1 A4 SE\ VSS1 VDD1 VSS1 A3 A2 SQ15 VSS1 VDD2 VSS2 VDD2 VSS2 CASU\ A1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 SQ8 DSF A0 SQ14 SQ13 SQ12 SQ11 SQ10 SQ9 DQ9 DQ8 QSF Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 VRAM Austin Semiconductor, Inc. GENERAL DESCRIPTION The SMJ55161A, a multiport-video random-access memory (RAM), is a high-speed, dual-port memory device. It consists of a dynamic RAM (DRAM) module organized as 262 144 words of 16 bits each interfaced to a serial-data register (serial-access memory [SAM]) organized as 512 words of 16 bits each. The SMJ55161A supports three basic types of operation: random access to and from the DRAM, serial access to/from the serial register, and transfer of data from any row in the DRAM to the serial register and vice versa. Except during transfer operations, the SMJ55161A can be accessed simultaneously and asynchronously from the DRAM and SAM ports. The SMJ55161A is equipped with several features designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel-draw rates are achieved by the device's (8 x 8) x 2 block-write feature. The block-write mode allows 16 bits of data (present in an on-chip color-data register) to be written to any combination of eight adjacent column-address locations. As many as 128 bits of data can be written to memory during each CAS\ cycle time. Also, on the DRAM port and SAM port, a write mask or a write-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write cycles without reloading. The SMJ55161A also offers byte control which can be applied in read cycles, write cycles, blockwrite cycles, load-write-mask-register cycles, and load-colorregister cycles. The SMJ55161A also offers extended-dataoutput (EDO) mode. The EDO mode is effective in both the page-mode and standard DRAM cycles. The SMJ55161A offers a split-register-transfer read (DRAM-to-SAM) feature for the serial register (SAM port) that enables real-time-register-load implementation for continuous serial-data streams without critical timing requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time register load (for example, loads done during CRT-retrace periods), the full-register mode of operation is retained to simplify system design. The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up to 50 MHz. During the split-register-transfer read operations, internal circuitry detects when the last bit position is accessed from the active half of the register and immediately transfers control to the opposite half. A separate output, QSF, is included to indicate which half of the serial register is active. All inputs, outputs, and clock signals on the SMJ55161 are compatible with Series 54/74 TTL. All address lines and data-in lines are latched on-chip to simplify system design. All dataout lines are unlatched to allow greater system flexibility. The SMJ55161A is offered in a 68-pin ceramic pin-gridarray package (GB suffix) and a 64-pin ceramic flatpack (HKC suffix). The SMJ55161A is supported by a broad line of graphic processors and control devices from Texas Instruments. See Table 2 and Table 4 for additional information. Additional features of the 55161A include MASKED FLASH WRITE which allows for data in color register to be written into all the memory locations of a selected row. SM55161A Production SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 VRAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM SM55161A Production SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 VRAM Austin Semiconductor, Inc. TABLE 1: DRAM & SAM FUNCTIONS RAS\ FALL FUNCTION CASx\ Reserved (do not use) CBR refresh (no reset) and stoppoint set 4 6 2 SM55161A Production DQ0-DQ151 3 CASx\ FALL DSF L H L H L H L DSF X X X X X X L ADDRESS RAS\ X Stop point X X Row Address Row Address 5 TRG\ L X X X L L H WE\ L L H H H H L CASX\ X X X X Tap Point Tap Point RAS\ X X X X X X L L L L H H H MNE CASL\ CODE CASU\ WE\ X --X X X X X Valid Data CBRS CBR CBRN RT SRT RWM CBR refresh (option reset) CBR refresh (no reset) 7 Full-register-transfer read Split-register-transfer read DRAM write (nonpersistent write-per-bit) DRAM block write (nonpersistent write-per-bit) DRAM write (persistent write-per-bit) DRAM block write (persistent write-per-bit) DRAM write (nonmasked) Row Column Write Address Address Mask H H L L H Block Row Write Column Address BWM Address Mask Mask A3-A8 Row Column Address Address Block Row Address Address A3-A8 Row Column Address Address Block Row Address Address A3-A8 Refresh Address Refresh Address Row Address Row Address Row Address X X Tap Point Tap Point X X Valid Data RWM H H L L L H H L L H X Column BWM Mask Valid Data Column Mask Write Mask Color Data X X --RW H H H L L X DRAM block write (nonmasked) 8 H H H L H X BW Load write-mask register Load color register Masked Write Transfer 9 H H H 9 H H L L H H H L L L H H L H H L H X X X X X Write Mask Write Mask Write Mask LMR LCR MWT MSWT FWM Masked Split Write Transfer H 9 Masked Flash Write Transfer H LEGEND: Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled X = Don't Care NOTES: 1. DQ0-DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later. 2. Logic L is selected when either or both CASL\ and CASU\ are low. 3. The column address and block address are latched on the first falling edge of CASx\. 4. CBRS cycle should be performed immediately after the power-up initialization cycle. 5. A0-A3, A8: don't care; A4-A7: stop-point code 6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. 7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. 8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle. 9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 VRAM Austin Semiconductor, Inc. PIN A0-A8 CASL\, CASU\ DQ DSF RAS\ SE\ SC SQ TRG\ WE\ QSF DRAM Row, column address Column-address strobe, DQ output enable DRAM data I/O, write mask Block-write enable Write-mask-register load enable Color-register load enable CBR (option reset) Row-address strobe TRANSFER Row address, Tap point Tap-address strobe Split-register-transfer enable SM55161A Production SAM TABLE 2: PIN DESCRIPTIONS VS. OPERATIONAL MODE Row-address strobe SQ output enable, QSF output enable Serial clock Serial-data output Transfer enable Serial-register status DQ output enable Write enable, write-pre-bit enable Special-function output Either make no external connection or tie to NC/GND system GND (VSS) VCC VSS 1 5V supply Ground 1 NOTES: 1. For proper device operation, all VCC pins must be connected to a 5-V supply, and all VSS pins must be tied to ground. address (A0-A8) Eighteen address bits are required to decode each one of the 262 144 storage cell locations. Nine row-address bits are set up on pins A0-A8 and latched onto the chip on the falling edge of RAS\. Nine column-address bits are set up on pins A0-A8 and latched onto the chip on the first falling edge of CASx\. All addresses must be stable on or before the falling edge of RAS\ and the first falling edge of CASx\. During the full-register-transfer read operation, the states of A0-A8 are latched on the falling edge of RAS\ to select one of the 512 rows where the transfer occurs. At the first falling edge of CASx\, the column-address bits A0-A8 are latched. The most significant column-address bit (A8) selects which half of the row is transferred to the SAM. The appropriate 8-bit column address (A0-A8) selects one of 512 tap points (starting positions) for the serial-data output. During the split-register-transfer read operation, an internal counter selects which half of the register is used. If the high half of the SAM is currently in use, the low half of the SAM is loaded with the low half of the DRAM half row and vice versa. Column address (A8) selects the DRAM half row. The remaining eight address bits (A0-A7) are used to select one of 256 possible starting locations within the SAM. SMJ55161A Rev. 1.6 03/05 row-address strobe (RAS\) RAS\ is similar to a chip enable so that all DRAM cycles and transfer cycles are initiated by the falling edge of RAS\. RAS\ is a control input that latches the states of the row address, WE\, TRG\, CASL\, CASU\, and DSF onto the chip to invoke DRAM and transfer-read/write functions of the SMJ55161A. column-address strobe (CASL, CASU) CASL\ and CASU\ are control inputs that latch the states of the column address and DSF to control DRAM and transfer functions of the SMJ55161A. CASx\ also acts as output enable for the DRAM output pins DQ0-DQ15. In DRAM operation, CASL\ enables data to be written to or read from the lower byte (DQ0-DQ7), and CASU\ enables data to be written to or from the upper byte (DQ8-DQ15). In transfer operations, address bits A0-A8 are latched at the first falling edge of CASx\ as the start position (tap) for the serial-data output (SQ0-SQ15). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 VRAM Austin Semiconductor, Inc. output enable/transfer select (TRG\) TRG\ selects either DRAM or transfer operation as RAS\ falls. For DRAM operation, TRG\ must be held high as RAS\ falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins DQ0-DQ15. For transfer operation, TRG\ must be brought low before RAS\ falls. SM55161A Production serial-data outputs (SQ0 -SQ15) Serial data is read from the SQ pins. The SQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state as long as the serial-enable pin, SE\, is high. The serial outputs are enabled when SE\ is brought low. write-mask select, write enable (WE) In DRAM operation, WE\ enables data to be written to the DRAM. WE\ is also used to select the DRAM write-per-bit mode. Holding WE\ low on the falling edge of RAS\ invokes the write-per-bit operation. The SMJ55161A supports both the nonpersistent write-per-bit mode and the persistent write-perbit mode. serial clock (SC) Serial data is accessed out of the data register during the rising edge of SC. The SMJ55161A is designed to work with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SCclock operating frequency. special-function select (DSF) The DSF input is latched on the falling edge of RAS\ or the first falling edge of CASx\, similar to an address. DSF determines which of the following functions are invoked on a particular cycle: * CBR refresh with reset (CBR) * CBR refresh with no reset (CBRN) * CBR refresh with no reset and stop-point set (CBRS) * Block write * Loading write-mask register for the persistent write-per-bit mode (LMR) * Loading color register for the block-write mode * Split-register-transfer read serial enable (SE) During serial-access operations, SE\ is used as an enable/ disable for the SQ outputs. SE\ low enables the serial-data output while SE\ high disables the serial-data output. SE\ is also used as an enable/disable for output pin QSF. IMPORTANT: While SE\ is held high, the serial clock is not disabled. External SC pulses increment the internal serialaddress counter regardless of the state of SE\. This ungated serial-clock scheme minimizes access time of serial output from SE\ low because the serial-clock input buffer and the serialaddress counter are not disabled by SE\. special-function output (QSF) QSF is an output pin that indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer is accessing the lower (least significant) 256 bits of the serial register (SAM). When QSF is high, the pointer is accessing the higher (most significant) 256 bits of the SAM. During full-register-transfer operations, QSF can change state upon completing the cycle. This state is determined by the tap point loaded during the transfer cycle. QSF is enabled by SE\; therefore, if SE\ is high, the QSF output is in the highimpedance state. DRAM data I/O, write mask data (DQ0-DQ15) DRAM data is written or read through the common I/O DQ pins. The 3-state DQ-output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. Data out is the same polarity as data in. During a normal access cycle, the outputs remain in the high-impedance state until TRG\ is brought low. Data appears at the outputs until TRG\ returns high, CASx\ returns high following RAS\ returning high, or RAS\ returns high following CASx\ returning high. The write mask is latched into the device through the random DQ pins by the falling edge of RAS\ and is used on all write-per-bit cycles. In a transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle. no connect / ground (NC/GND) NC/GND must be tied to system ground or left floating for proper device operation. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 VRAM Austin Semiconductor, Inc. TABLE 3: DRAM FUNCTIONS RAS\ FALL FUNCTION CASx\ Reserved (do not use) CBR refresh (no reset) and stoppoint set 4 6 2 SM55161A Production ADDRESS RAS\ X Stop point X X 5 CASx\ FALL DSF L H L H L DSF X X X X L DQ0-DQ151 3 TRG\ L X X X H WE\ L L H H L CASX\ X X X X RAS\ X X X X L L L L H MNE CASL\ CODE CASU\ WE\ X --X X X Valid Data CBRS CBR CBRN RWM CBR refresh (option reset) CBR refresh (no reset) 7 DRAM write (nonpersistent write-per-bit) DRAM block write (nonpersistent write-per-bit) DRAM write (persistent write-per-bit) DRAM block write (persistent write-per-bit) DRAM write (nonmasked) Row Column Write Address Address Mask H H L L H Block Row Write Column Address BWM Address Mask Mask A3-A8 Row Column Address Address Block Row Address Address A3-A8 Row Column Address Address Block Row Address Address A3-A8 Refresh Address Refresh Address X X X Valid Data RWM H H L L L H H L L H X Column BWM Mask Valid Data Column Mask Write Mask Color Data RW H H H L L X DRAM block write (nonmasked) 8 H H H L H X BW Load write-mask register Load color register H H H H H H H H L H X X LMR LCR LEGEND: Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled X = Don't Care NOTES: 1. DQ0-DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later. 2. Logic L is selected when either or both CASL\ and CASU\ are low. 3. The column address and block address are latched on the first falling edge of CASx\. 4. CBRS cycle should be performed immediately after the powerup initialization cycle. 5. A0-A3, A8: don't care; A4-A7: stop-point code 6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. 7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. 8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle. 9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 VRAM Austin Semiconductor, Inc. enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. This mode eliminates the time required for row-address setup, row-address hold, and address multiplex. The maximum RAS\ low time and CAS\ page cycle time used determine the number of columns that can be accessed. Unlike conventional page-mode operations, the enhanced page mode allows the SMJ55161A to operate at a higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx\ transitions low. A valid column address can be presented immediately after the row-address hold time has been satisfied, usually well in advance of the falling edge of CASx\. In this case, data is obtained after ta(C) MAX (access time from CASx\ low) if ta(CA) MAX (access time from column address) has been satisfied. SM55161A Production need to be refreshed consecutively as long as the entire refresh is completed within the required time period, trf(MA). The output buffers remain in the high-impedance state during the CBR refresh cycles regardless of the state of TRG\. hidden refresh A hidden refresh is accomplished by holding both CASL\ and CASU\ low in the DRAM read cycle and cycling RAS\. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh. RAS-only refresh A RAS\-only refresh is accomplished by cycling RAS\ at every row address. Unless CASx\ and TRG\ are low, the output buffers remain in the high-impedance state to conserve power. Externally-generated addresses must be supplied during RAS\only refresh. Strobing each of the 512 row addresses with RAS\ causes all bits in each row to be refreshed. REFRESH CAS-before-RAS (CBR) refresh CBR refreshes are accomplished by bringing either or both CASL\ and CASU\ low earlier than RAS\. The external row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode. The CBRN and CBRS refreshes (no reset) do not end the persistent write-per-bit mode or the stoppoint mode. The 512 rows of the DRAM do not necessarily extended data output The SMJ55161A features EDO during DRAM accesses. While RAS\ and TRG\ are low, the DRAM output remains valid. The output remains valid even when CASx\ returns high until WE\ is low, TRG\ is high, or both CASx\ and RAS\ are high (see Figure 1 and Figure 2). The EDO mode functions during all read cycles including DRAM read, page-mode read, and readmodify-write cycles (see Figure 3). FIGURE 1: DRAM Read Cycle With RAS\-Controlled Output SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 2: DRAM Read Cycle With CASx\-Controlled Output FIGURE 3: DRAM Page-Read Cycle with Extended Output SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 VRAM Austin Semiconductor, Inc. byte operation Byte operation can be applied in DRAM-read cycles, write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. In byte operation, the column address (A0-A8) is latched at the first falling edge of CASx\. In read cycles, CASL\ enables the lower byte (DQ0-DQ7) and CASU\ enables the upper byte (DQ8-DQ15) (see Figure 4). In byte-write operation, CASL enables data to be written to the lower byte (DQ0-DQ7), and CASU\ enables data to be written to the upper byte (DQ8-DQ15). In an early write cycle, WE is brought low prior to both CASx\ signals, and data setup and hold times for DQ0 -DQ15 are referenced to the first falling edge of CASx\ (see Figure 5). For late-write or read-modify-write cycles, WE\ is brought low after either or both CASL\ and CASU\ fall. The data is strobed in with data setup and hold times for DQ0 -DQ15 referenced to WE\ (see Figure 6). SM55161A Production FIGURE 4: Example of a Byte-Read Cycle SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 VRAM Austin Semiconductor, Inc. FIGURE 5: Example of an Early-Write Cycle SM55161A Production FIGURE 6: Example of a Late-Write Cycle SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 VRAM Austin Semiconductor, Inc. write-per-bit The write-per-bit feature allows masking any combination of the 16 DQs on any write cycle. The write-per-bit operation is invoked when WE\ is held low on the falling edge of RAS\. If WE\ is held high on the falling edge of RAS\, the write operation is performed without any masking. The SMJ55161A offers two write-per-bit modes: nonpersistent write-per-bit and persistent write-per-bit. SM55161A Production nonpersistent write-per-bit When WE\ is low on the falling edge of RAS\, the write mask is reloaded. A 16-bit binary code (the write-per-bit mask) is input to the device through the DQ pins and latched on the falling edge of RAS\. The write-per-bit mask selects which of the 16 I/Os are to be written and which are not. After RAS\ has latched the on-chip write-per-bit mask, input data is driven onto the DQ pins and is latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later. CASL\ enables the lower byte (DQ0-DQ7) to be written through the mask and CASU\ enables the upper byte (DQ8-DQ15) to be written through the mask. If a data low (write mask = 0) is strobed into a particular I/O pin on the falling edge of RAS\, data is not written to that I/O. If a data high (write mask = 1) is strobed into a particular I/O pin on the falling edge of RAS\, data is written to that I/O (see Figure 7). FIGURE 7: Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 VRAM Austin Semiconductor, Inc. persistent write-per-bit The persistent write-per-bit mode is initiated by performing a load-write-mask-register (LMR) cycle. In the persistent write-per-bit mode, the write-per-bit mask is overwritten but remains valid over an arbitrary number of write cycles until another LMR cycle is performed or power is removed. The LMR cycle is performed using DRAM write-cycle timing with DSF held high on the falling edge of RAS\ and held low on the first falling edge of CASx\. A binary code is input to SM55161A Production the write-mask register via the random I/O pins and latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later. Byte write control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode can then be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data on the falling edge of RAS\ is ignored. When the device is set to the persistent write-per-bit mode, it remains in this mode and is reset only by a CBR refresh (option-reset) cycle (see Figure 8). FIGURE 8: Example of a Persistent Write-Per-Bit Operation SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 VRAM Austin Semiconductor, Inc. block write The block-write feature allows up to 128 bits of data to be written simultaneously to one row of the memory array. This function is implemented as eight columns by eight DQs and repeated in two halves. In this manner, each of the two 2M-bit halves can have up to eight consecutive columns written at a time with up to eight DQs per column (see Figure 9). Each 2M-bit half has a 8-bit column mask to mask off and prevent any or all of the eight columns from being written with SM55161A Production data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write operation to provide write-masking options. The DQ data is provided by 8 bits from the on-chip color register. Bits 0-7 from the 16-bit write-mask register, bits 0 -7 from the 16-bit column-mask register, and bits 0 -7 from the 16-bit color-data register configure the block write for the first half, while bits 8 - 15 of the corresponding register control the other half in a similar fashion (see Figure 10). FIGURE 9: Block-Write Operation SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 VRAM Austin Semiconductor, Inc. FIGURE 10: Block-Write With Masks SM55161A Production SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 VRAM Austin Semiconductor, Inc. block write (continued) A set of eight columns makes a block, resulting in 64 blocks along one row. Block 0 comprises columns 0 -7, block 1 comprises columns 7 -15, block 2 comprises columns 16 -23, etc., as shown in Figure 11. During block-write cycles, only the six most significant column addresses (A3-A8) are latched on the first falling edge of CASx to decode one of the 64 blocks. Address bits A0-A2 are ignored. Each 2M-bit half has the same block selected. A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the first falling edge of CASx\. As in a DRAM write operation, CASL\ and CASU\ enable the corresponding lower and upper DRAM DQ bytes to be written. The column-mask data is input via the DQs and is latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later. The 16-bit color-data register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section for details on use of the write-mask capability, allowing additional performance options. Example of block write: Block-write column address = 110000000 (A0-A8 from left to right) bit 0 1011 1110 1111 1st Quad bit 15 0111 1011 1010 4th Quad SM55161A Production Column-address bits A0 and A2 are ignored. Block 0 (columns 0 -7) is selected for each 2M-bit half. The first half has DQ0-DQ2 written with bits 0-2 from the color-data register (101) to first four columns of block 0. DQ3 is not written and retains its previous data due to write-mask-register-bit 3 being 0. DQ4-DQ7 has all four columns masked off due to column-mask bits 4-7 being 0 so that no data is written. The second half (DQ8-DQ11 ) has its four DQs written with bits 8 -11 from the color-data register (1100) to columns 1-3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to column-mask-register-bit 8 being 0. DQ12-DQ15 has DQ12, DQ14, and DQ15 written with bits 12, 14, and 15 from the color-data register to column 0 and column 2 of its block 0. DQ13 retains its previous data on all columns due to the write mask. Columns 1 and 3 retain their previous data on all DQs due to the column mask. If the previous data for DQ12-DQ15 is all 0s, the upper half (DQ12-DQ15) contains the data pattern shown in Figure 12 after the blockwrite operation shown in the previous example. FIGURE 12: Example of Upper DQ12-DQ15 After A Block-Write Operation With Previous Data Of 0 Color-data register = Write-mask register = Column-mask register = 1011 1111 0000 2nd Quad 1100 1111 0111 3rd Quad FIGURE 11: Block Columns Organization SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 VRAM Austin Semiconductor, Inc. load color register The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high on the falling edges of RAS\, CASL\, and CASU\. The color register is loaded from pins DQ0 -DQ15, which are latched on either the first SM55161A Production falling edge of CASx\ or the falling edge of WE\, whichever occurs later. If only one CASx\ is low, only the corresponding byte of the color register is loaded. When the color register is loaded, it retains data until power is lost or until another loadcolor-register cycle is performed (see Figure 13 and Figure 14). FIGURE 13: Example of Block Writes FIGURE 14: Example Of A Persistent Block Write Legend: 1. Refresh address 2. Row address 3. Block address (A3-A8) is latched on the first falling edge of CASx\. 4. Color-register data 5. Write-mask data: DQ0-DQ15 are latched on the falling edge of RAS\. 6. Column-mask data: DQi-DQi+7 (i = 0, 8) are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 VRAM Austin Semiconductor, Inc. DRAM-to-SAM transfer operation During the DRAM-to-SAM transfer operation, one row (512 columns) in the DRAM array is selected to be transferred to the 512-bit serial-data register. The transfer operation is invoked by TRG\ being brought low and WE\ being held high on the falling edge of RAS\. The state of DSF, which is latched on the falling edge of RAS\, determines whether the fullregister-transfer read operation or the split-register-transfer read operation is performed (see Table 4). SM55161A Production full-register-transfer read A full-register-transfer read operation loads data from a selected half of a row in the DRAM into the SAM. TRG\ is brought low and latched at the falling edge of RAS\. Nine rowaddress bits (A0-A8) are also latched at the falling edge of RAS\ to select one of the 512 rows available for the transfer. The nine column-address bits (A0- A8) are latched at the first falling edge of CASx\. Address bits A0-A8 select one of the SAM's 512 available tap points from which the serial data is read out. A full-register-transfer read can be performed in three ways: early load, real-time load (or midline load), or late load. Each of these offers the flexibility of controlling the TRG\ trailing edge in the full-register-transfer read cycle (see Figure 15). TABLE 4: SAM Fuction Table RAS\ FALL FUNCTION CASx\ Full-register-transfer Read H 1 CASx\ FALL DSF L DSF X ADDRESS RAS\ Row Address Row Address CASX\ Tap Point Tap Point DQ0-DQ15 RAS\ X TRG\ L WE\ H MNE CASx\ CODE WE\ X RT Split-register-transfer Read H L H H X X X SRT LEGEND: X = Don't Care NOTES: 1. Logic L is selected when either CASL\ or CASU\ are low. FIGURE 15: Example of Full-Register-Transfer Read Operations SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19 VRAM Austin Semiconductor, Inc. split-register-transfer read The SMJ55161A features two types of bidirectional data transfer capability between DRAM and SAM. 1) Conventional (non split) transfer: 512 words by 16 bits of data can be loaded from DRAM to SAM (Read transfer), or from SAM to DRAM (write transfer). 2) Split transfer: 256 words by 16 bits of data can be loaded from the lower/upper half of the DRAM to the lower/uppper half of the SAM (Split read transfer), or from the lower/upper half to SAM to the lower/upper half of DRAM (Split write transfer). The conventional transfer and split transfer modes are controlled by the DSF input signal. Data transfer is invoked by holding the TRG\ signal "low" at the falling edge of RAS\. The SMJ55161A supports 4 types of transfer operations: Read transfer, Split read transfer, Write transfer and Split write transfer as shown in the truth table. The type of transfer operation is determined by the state of CAS\, WE\, and DSF latched at the falling edge of RAS\. During conventional transfer operations, the SAM port is switched from input to SM55161A Production output mode (Read transfer), or output to input mode (Write transfer). It remains unchanged during split transfer operation (Split read transfer or Split write transfer). Both DRAM and SAM are divided by the most significant row address (AX8), as shown in Figure 16. Therefore, no data transfer between AX8=0 side DRAM and AX8=1 side DRAM can be provided through the SAM. Care must be taken if the split read transfer on AX8=1 side (or AX8=0 side) is provided after the read transfer or the split read transfer, is provided on AX8=0 side (or AX8=1 side). QSF indicates which half of the register is being accessed during serial-access operation. When QSF is low, the serialaddress pointer is accessing the lower (least significant) 256 bits of the SAM. When QSF is high, the pointer is accessing the higher (most significant) 256 bits of the SAM. QSF changes state upon completing a full-register-transfer-read cycle. The tap point loaded during the current transfer cycle determines the state of QSF. QSF also changes state when a boundary between two register halves is reached. FIGURE 16: DRAM and SAM Configuration SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 20 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 17: Example Of A Split-Register-Transfer Read After A FullRegister-Transfer Read FIGURE 18: Example Of Successive Split-Register-Transfer-Read Operations SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 21 VRAM Austin Semiconductor, Inc. serial-read operation The serial-read operation can be performed through the SAM port simultaneously and asynchronously with DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown in Figure 19. For split-register-transfer-read operation, serial data can be read out from the active half of the SAM by clocking SC starting at the tap point loaded by the preceding splitregister-transfer cycle. The serial pointer then proceeds sequentially to the most significant bit of the half, bit 255 or bit 511. If there is a split-register-transfer read to the inactive half during this period, the serial pointer points next to the tap point location loaded by that split-register transfer (see Figure 20). SM55161A Production If there is no split-register-transfer read to the inactive half during this period, the serial pointer points next to bit 256 or bit 0, respectively (see Figure 21). split-register programmable stop point The SMJ55161A offers a programmable stop-point mode for split-register-transfer read operations. This mode can be used to improve two-dimensional drawing performance in a nonscanline data format. For a split-register-transfer-read operation, the stop point is defined as a register location at which the serial output stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point mode, the SAM is divided into partitions whose length is programmed via row addresses A4-A7 in a CBR set (CBRS) cycle. The last serial-address location of each partition is the stop point (see Figure 22). SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 22 VRAM Austin Semiconductor, Inc. split-register programmable stop point (continued) Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is enabled by holding CASx\ and WE\ low and DSF high on the falling edge of RAS\. The falling edge of RAS\ also latches row addresses A4-A7 which are used to define the SAM's partition length. The other rowaddress inputs are don't cares. Stop-point mode should be initiated after the initialization cycles are performed (see Table 5). SM55161A Production In stop-point mode, the tap point loaded during the splitregister-transfer read cycle determines the SAM partition in which the serial output begins and at which stop point the serial output stops coming from one half of the SAM and switches to the opposite half of the SAM (see Figure 23). The stop-point mode of the previous revision 55161 is designed to be compatible with both 256-bit SAM and 512-bit SAM devices like the 55161A. IMPORTANT: For proper device operation, a stop-pointmode (CBRS) cycle should be initiated immediately after the power-up initialization cycles are performed. TABLE 5: Programming Code for Stop-Point Mode MAX PARTITION LENGTH 16 32 64 128 256 ADDRESS AT RAS\ IN CBRS CYCLE A8 X X X X X A7 L L L L H A6 L L L H H A5 L L H H H A4 L H H H H A0 - A3 X X X X X 16 8 4 2 1 31, 63, 95, 127, 159, 191, 223, 255, 287, 319, 351, 383, 415, 447, 479, 511 63, 127, 191, 255, 319, 383, 447, 511 127, 255, 383, 511 255, 511 255 NUMBER OF PARTITIONS STOP-POINT LOCATIONS FIGURE 23: Example of Split-Register Operation With Programmable Stop Points SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 23 VRAM Austin Semiconductor, Inc. power up To achieve proper device operation, an initial pause of 200 ms is required after power up followed by a minimum of eight RAS\ cycles or eight CBR cycles to initialize the DRAM port. A full- SM55161A Production register-transfer-read cycle and two SC cycles are required to initialize the SAM port. After initialization, the internal state of the SMJ55161A is as shown in Table 6. TABLE 6: Internal State of SMJ55161A STATE QSF Write Mode Write-mask Register Color Register Serial-Register Tap Point SAM Port STATE AFTER INITIALIZATION Defined by the transfer cycle during initialization Nonpersistent Mode Undefined Undefined Defined by the transfer cycle during initialization Output Mode ABSOLUTE MAXIMUM RATINGS* Supply voltage range, VCC**........................................-1V to +7 V Voltage range on any pin................................................-1V to +7 V Short-circuit output current.......................................................50mA Power dissipation.........................................................................1.1W Operating free-air temperature range, TA...................-55C to 125C Storage temperature range, Tstg..................................-65C to 150C *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **All voltage values are with respect to VSS. RECOMMENDED OPERATING CONDITIONS CONDITION Supply Voltage Supply Voltage High-level input voltage Low-level input voltage 1 SYMBOL VCC VSS VIH VIL TA MIN 4.5 NOM 5 0 MAX 5.5 UNIT V V 2.4 -0.5 -55 VCC +0.5 0.8 125 V V C Operating free-air temperature NOTES: 1. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 24 VRAM Austin Semiconductor, Inc. SM55161A Production ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED) PARAMETER High-level output voltage Low-level output voltage SYMBOL VOH VOL CONDITIONS VOH = -1 mA VOL = 2 mA VCC = 5.5V, Input current (leakage) II 3 SAM PORT -70 MIN MAX 2.4 0.4 -75 MIN MAX 2.4 0.4 -80 MIN MAX UNIT 2.4 0.4 V V VI = 0V to 5.8V, All other pins at 0V to VCC 10 10 10 A Output current (leakage) Operating current Operating current Standby current Standby current 2 2 IO ICC1 ICC1A ICC2 ICC2A ICC3 ICC3A ICC4 ICC4A ICC5 ICC5A ICC6 ICC6A VCC = 5.5V, VO = 0V to VCC See note 4 tc(SC) = MIN All clocks = VCC tc(SC) = MIN See note 4 tc(SC) = MIN tc(P) = MIN 5 5 5 10 Standby Active Standby Active Standby Active Standby Active Standby 140 180 12 60 130 175 140 190 110 150 120 170 10 130 170 12 55 120 165 130 180 100 140 120 160 10 120 160 12 50 115 155 120 170 95 130 110 150 A mA mA mA mA mA mA mA mA mA mA mA mA RAS\-only refresh current RAS\-only refresh current Page-mode current 2 Page-mode current2 CBR current CBR current Data-transfer current Data-transfer current tc(SC) = MIN See note 4 tc(SC) = MIN See note 4 tc(SC) = MIN 5 Active Standby Active NOTES: 1. 2. 3. 4. 5. For conditions shown as MAX/MIN, use the appropriate value specified in the timing requirements. Measured with outputs open. SE\ is disabled for SQ output leakage tests. Measured with one address change while RAS\ = VIL; tc(rd), tc(W), tc(TRD) = MIN. Measured with one address change while CASx\ = VIH. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 25 VRAM Austin Semiconductor, Inc. SM55161A Production CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE* PARAMETER Input capacitance, address inputs Input capacitance, address-strobe inputs Input capacitance, write-enable input Input capacitance, serial clock Input capacitance, serial enable Input capacitance, special function Input capacitance, transfer-register input Output capacitance, SQ and DQ Output capacitance, QSF SYMBOL Ci(A) Ci(RC) Ci(W) Ci(SC) Ci(SE) Ci(DSF) Ci(TRG) CO(O) CO(QSF) MIN TYP 5 8 7 6 7 7 7 12 10 MAX 10 10 10 10 10 10 10 15 12 UNIT pF pF pF pF pF pF pF pF pF NOTES: *VCC = 5V 0.5V, and the bias on pins under test is 0V. SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE1 PARAMETER Access time from CASx\ Access time from column address Access time from CASx\ high Access time from RAS\ Access time of DQ from TRG\ low Access time of SQ from SC high Access time of SQ from SE\ low Disable time, random output from CASx\ high Disable time, random output from RAS\ high 3 3 3 SYMBOL ta(C) ta(CA) ta(CP) ta(R) ta(G) ta(SQ) ta(SE) tdis(CH) tdis(RH) tdis(G) tdis(WL) tdis(SE) CONDITIONS2 -70 MIN MAX 17 -75 MIN MAX 20 38 43 75 20 23 18 0 0 0 0 0 20 20 20 25 18 -80 MIN MAX 20 40 45 80 20 25 20 0 0 0 0 0 20 20 20 25 20 UNIT ns ns ns ns ns ns ns ns ns ns ns ns td(RLCL) = MAX 35 40 70 17 CL = 30 pF CL = 30 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 30 pF 0 0 0 0 0 20 17 17 17 17 17 15 Disable time, random output from TRG\ high Disable time, random output from WE\ low Disable time, serial output from SE\ high NOTES: 1. Switching times for RAM-port output are measured with a load equivalent to one TTL load and 50pF. Data-out reference level: VOH/VOL = 2V/0.8V. Switching times for SAM-port output are measured with a load equivalent to one TTL load and 30pF. Serial-data out reference level: VOH/VOL = 2V/0.8V. 2. For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. 3. tdis(CH), tdis(RH), tdis(G), tdis(WL), and tdis(SE) are specified when the output is no longer driven. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 26 VRAM Austin Semiconductor, Inc. SM55161A Production TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE1 PARAMETER Cycle time, read Cycle time, write Cycle time, read-modify-write Cycle time, page-mode read, write Cycle time, page-mode read-modify-write Cycle time, transfer read Cycle time, serial clock 2 SYMBOL MIN tc(rd) tc(W) tc(rdW) tc(P) tc(RDWP) tc(TRD) tc(SC) tw(CH) tw(CL) tw(RH) tw(RL) tw(WL) tw(TRG) tw(SCH) tw(SCL) tw(GH) tw(RL)P tsu(CA) tsu(SFC) tsu(RA) tsu(WMR) tsu(DQR) tsu(TRG) tsu(SFR) tsu(DCL) tsu(DWL) tsu(rd) tsu(WCL) tsu(WCH) tsu(WRH) th(CLCA) th(SFC) th(RA) th(TRG) th(RWM) th(RDQ) 124 124 170 35 74 130 20 10 15 50 70 10 17 7 7 20 70 0 0 0 0 0 0 0 0 0 0 0 15 17 10 12 10 12 12 12 -70 MAX MIN 140 140 188 48 88 140 24 10 -75 MAX MIN 150 150 200 50 90 150 30 10 -80 MAX UNIT ns ns ns ns ns ns ns ns Pulse duration, CASx\ high Pulse duration, CASx\ low Pulse duration, RAS\ high Pulse duration, RAS\ low Pulse duration, WE\ low Pulse duration, TRG\ low Pulse duration, SC high Pulse duration, SC low Pulse duration, TRG\ high Pulse duration, RAS\ low (page mode) Setup time, column address before CASx\ low Setup time, DSF before CASx\ low Setup time, row address before RAS\ low Setup time, WE\ before RAS\ low Setup time, DQ before RAS\ low Setup time, TRG\ high before RAS\ low Setup time, DSF low before RAS\ low Setup time, data valid before CASx\ low Setup time, data valid before WE\ low Setup time, read command, WE\ high before CASx\ low Setup time, early-write command, WE\ low before CASx\ low Setup time, WE\ low before CASx\ high, write Setup time, WE\ low before RAS\ high, write Hold time, column address after CASx\ low Hold time, DSF after CASx\ low Hold time, row address after RAS\ low Hold time, TRG\ after RAS\ low Hold time, write mask after RAS\ low Hold time, DQ after RAS\ low (write-mask operation) SMJ55161A Rev. 1.6 03/05 3 10,000 20 55 10,000 20 60 10,000 ns ns 4 10,000 75 13 20 9 9 20 10,000 80 15 20 10 10 20 10,000 ns ns ns ns ns ns 100,000 75 0 0 0 0 0 0 0 0 0 0 0 18 20 13 15 10 15 15 15 100,000 80 0 0 0 0 0 0 0 0 0 0 0 20 20 15 15 10 15 15 15 100,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 27 VRAM Austin Semiconductor, Inc. SM55161A Production -75 -80 MAX MIN MAX UNIT 10 35 15 35 15 0 0 15 35 10 2 35 0 80 15 5 20 50 50 20 40 40 105 65 5 0 20 15 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 35 15 20 25 5 -10 60 20 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)1 PARAMETER Hold time, DSF after RAS\ low Hold time, column address valid after RAS\ low Hold time, data valid after CASx\ low Hold time, data valid after RAS\ low Hold time, data valid after WE\ low Hold time, read, WE\ high after CASx\ high Hold time, read, WE\ high after RAS\ high Hold time, write, WE\ low after CASx\low Hold time, write, WE\ low after RAS\ low Hold time, TRG\ high after WE\ low Hold time, SQ valid after SC high Hold time, DSF after RAS\ low Hold time, output valid after CASx\ low Delay time, RAS\ low to CASx\ high Delay time, CASx\ high to RAS\ low Delay time, CASx\ low to RAS\ high Delay time, CASx\ low to WE\ low 9,10 11 7 5 6 6 5 5 SYMBOL MIN th(SFR) th(RLCA) th(CLD) th(RLD) th(WLD) th(CHrd) th(RHrd) th(CLW) th(RLW) th(WLG) th(SHSQ) th(RSF) th(CLQ) td(RLCH) See Note 8 td(RLCH) td(CHRL) td(CLRH) td(CLWL) td(RLCL) td(CARH) td(CACH) td(RLWL) 9 -70 MAX MIN 10 33 15 35 15 0 0 15 35 10 2 35 0 75 13 5 20 48 10 30 12 30 12 0 0 12 30 10 2 30 0 70 10 7 17 40 15 35 35 90 55 5 0 20 15 55 70 12 15 20 5 -10 50 15 35 50 Delay time, RAS\ low to CASx\ low 20 38 38 100 63 5 0 20 15 58 75 15 20 23 5 -10 55 18 Delay time, column address valid to RAS\ high Delay time, column address valid to CASx\ high Delay time, RAS\ low to WE\ low 9 Delay time, column address valid to WE\ low Delay time, CASx\ low to RAS\ low 8 8 td(CAWL) td(CLRL) td(RHCL) td(CLGH) td(GHD) td(RLTH) 13 Delay time, RAS\ high to CASx\ low Delay time, CASx\ low to TRG\ high for DRAM read cycles Delay time, TRG\ high before data applied at DQ Delay time, RAS\ low to TRG\ high 12 Delay time, RAS\ low to first SC high after TRG\ high Delay time, RAS\ low to column address valid Delay time, TRG\ low to RAS\ high td(RLSH) td(RLCA) td(GLRH) Delay time, CASx\ low to first SC high after TRG\ high Delay time, SC high to TRG\ high 12, 13 12 13 td(CLSH) td(SCTR) td(THRH) td(THRL) td(THSC) Delay time, TRG\ high to RAS\ high Delay time, TRG\ high to RAS\ low Delay time, TRG\ high to SC high SMJ55161A Rev. 1.6 03/05 14 12 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 28 VRAM Austin Semiconductor, Inc. SM55161A Production TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)1 PARAMETER Delay time, RAS\ high to last (most significant) rising edge of SC before boundary switch during split-register-transfer read cycles Delay time, CASx\ low to TRG\ high in read-time-transfer read cycles Delay time, column address to first SC in early-load-transfer read cycles Delay time, column address to TRG\ high in real-time-transfer read cycles Delay time, data to CASx\ low Delay time, data to TRG\ low Delay time, last (most significant) rising edge of SC to RAS\ low before boundary switch during split-register-transfer read cycles Delay time, last (127 or 255) rising edge of SC to QSF switching at the boundary during split-register-transfer read cycles 15 15 -70 -75 -80 SYMBOL MIN MAX MIN MAX MIN MAX UNIT td(RHMS) td(CLTH) td(CASH) td(CAGH) td(DCL) td(DGL) td(MSRL) td(SCQSF) td(CLQSF) td(GHQSF) td(RLQSF) trf(MA) tt 3 20 17 25 20 0 0 20 25 30 25 70 8 25 3 20 15 28 20 0 0 20 28 33 28 73 8 25 3 20 15 30 20 0 0 20 30 35 30 75 8 25 ns ns ns ns ns ns ns ns ns ns ns ms ns Delay time, CASx\ low to QSF switching in transfer-read cycles Delay time, TRG\ high to QSF switching in transfer-read cycles Delay time, RAS\ lwo to QSF switching in transfer-read cycles Refresh time interval, memory Transition time 15 15 NOTE: 1. Timing measurements are referenced to VIL MAX and VIH MIN. 2. Cycle time assumes tt = 3 ns. 3. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the transition times, this can require additional CASx\ low time [tw(CL)]. 4. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the transition times, this can require additional RAS\ low time [tw(RL)]. 5. The minimum value is measured when td(RLCL) is set to td(RLCL) MIN as a reference. 6. Either th(RHrd) or td(CHrd) must be satisfied for a read cycle. 7. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle. 8. CBR refresh operation only. 9. Read-modify-write operation only. 10. TRG\ must disable the output buffers prior to applying data to the DQ pins. 11. The maximum value is specified only to assure RAS\ access time. 12. Real-time-load transfer read or late-load-transfer read cycle only. 13. Early-load-transfer read cycle only. 14. Full-register-(read) transfer cycles only. 15. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference level is VOH / VOL = 2 V/0.8 V. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 29 VRAM Austin Semiconductor, Inc. SAM TO DRAM WRITE TRANSFER & SERIAL IN TIMINGS PARAMETER Last SC to RAS\ set-up time (serial input) RAS\ to serial input delay time Serial input set-up time Serial input hold time Serial input to SE\ delay time Serial input to first SC delay time Serial write enable to set-up time Serial write enable to hold time Serial write disable to set-up time Serial write disable to hold time SYMBOL tSRS tSDD tSDS tSDH tSZE tSZS tSWS tSWH tSWiS tSWiH -70 25 35 0 0 0 0 0 10 0 10 -75 25 40 0 0 0 0 0 12 0 12 -80 25 45 0 0 0 0 0 12 0 12 UNITS ns ns ns ns ns ns ns ns ns ns SM55161A Production SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 30 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 24: READ-CYCLE TIMING WITH CASx\-CONTROLLED OUTPUT SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 31 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 25: READ-CYCLE TIMING WITH RAS\-CONTROLLED OUTPUT SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 32 VRAM Austin Semiconductor, Inc. FIGURE 26: EARLY-WRITE-CYCLE TIMING SM55161A Production TABLE 7: EARLY-WRITE-CYCLE STATE TABLE CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit 1 H L L STATE 2 3 Don't Care Valid Data Write Mask Valid Data Don't Care Valid Data SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 33 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 27: LATE-WRITE-CYCLE TIMING (OUTPUT-ENABLE-CONTROLLED WRITE) TABLE 8: LATE-WRITE-CYCLE STATE TABLE CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit 1 H L L STATE 2 3 Don't Care Valid Data Write Mask Valid Data Don't Care Valid Data SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 34 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 28: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD) NOTES: 1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 35 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 29: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (LATE-WRITE LOAD) NOTES: 1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 36 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 30: READ-WRITE/READ-MODIFY-WRITE-CYCLE TIMING TABLE 9: READ-WRITE/READ-MODIFY-WRITE-CYCLE STATE TABLE CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit 1 H L L STATE 2 3 Don't Care Valid Data Write Mask Valid Data Don't Care Valid Data SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 37 VRAM Austin Semiconductor, Inc. FIGURE 31: ENHANCED-PAGE-MODE READ-CYCLE TIMING SM55161A Production NOTES: A. Access time is ta(CP) or ta(CA) dependent. B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. C. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS\ and CASx\ to select the desired write mode (normal, block write, etc.). SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 38 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 32: ENHANCED-PAGE-MODE WRITE-CYCLE TIMING NOTES: A. Referenced to the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing specifications. To ensure page-mode cycle time, TRG\ must remain high throughout the entire page-mode operation if the late write feature is used. If the early write-cycle timing is used, the state of TRG\ is a don't care after the minimum period th(TRG) from the falling edge of RAS\.. TABLE 10: ENHANCED-PAGE-MODE WRITE-CYCLE STATE TABLE CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit Load-write mask on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later. 1 1 L L L H 2 L L L L STATE 3 4 H Don't Care L Write Mask L Don't Care H 5 Valid Data Valid Data Valid Data Don't Care Write Mask NOTES: 1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is a don't care during this cycle. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 39 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 33: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE TIMING NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated. TABLE 11: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE STATE TABLE CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit Load-write mask on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later. 1 1 L L L H 2 L L L L STATE 3 4 5 H Don't Care Valid Data L Write Mask Valid Data L Don't Care Valid Data H Don't Care Write Mask NOTES: 1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is a don't care during this cycle. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 40 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 34: ENHANCED-PAGE-MODE READ-/WRITE-CYCLE TIMING NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS\ and CASx\ to select the desired write mode (normal, block write, etc.). SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 41 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 35: LOAD-COLOR-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD) SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 42 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 36: LOAD-COLOR-REGISTER-CYCLE TIMING (LATE-WRITE LOAD) SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 43 VRAM Austin Semiconductor, Inc. FIGURE 37: BLOCK-WRITE-CYCLE TIMING (EARLY WRITE) SM55161A Production SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 44 VRAM Austin Semiconductor, Inc. TABLE 12: BLOCK-WRITE-CYCLE STATE TABLE CYCLE Block-write operation (nonmasked) Block-write operation with nonpersistent write-per-bit Block-write operation with persistent write-per-bit 1 H L L STATE 2 3 Don't Care Valid Data Write Mask Valid Data Don't Care Valid Data SM55161A Production Write-mask data 0: I/O write disable 1: I/O write enable DQ Column-mask data DQi - DQi + 7 0: column-write disable (i = 0,8) 1: column-write enable COLUMN MASK DATA DQ0-15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 COLUMN MASK DATA Column 0 (A0 = 0, A1 = 0, A2 = 0) Column 1 (A0 = 1, A1 = 0, A2 = 0) Column 2 (A0 = 0, A1 = 1, A2 = 0) Column 3 (A0 = 1, A1 = 1, A2 = 0) Column 4 (A0 = 0, A1 = 0, A2 = 1) Column 5 (A0 = 1, A1 = 0, A2 = 1) Column 6 (A0 = 0, A1 = 1, A2 = 1) Column 7 (A0 = 1, A1 = 1, A2 = 1) Column 0 (A0 = 0, A1 = 0, A2 = 0) Column 1 (A0 = 1, A1 = 0, A2 = 0) Column 2 (A0 = 0, A1 = 1, A2 = 0) Column 3 (A0 = 1, A1 = 1, A2 = 0) Column 4 (A0 = 0, A1 = 0, A2 = 1) Column 5 (A0 = 1, A1 = 0, A2 = 1) Column 6 (A0 = 0, A1 = 1, A2 = 1) Column 7 (A0 = 1, A1 = 1, A2 = 1) Lower Byte Low: Mask High: No Mask Upper Byte Low: Mask High: No Mask SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 45 VRAM Austin Semiconductor, Inc. FIGURE 38: BLOCK-WRITE-CYCLE TIMING (LATE WRITE) SM55161A Production SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 46 VRAM Austin Semiconductor, Inc. TABLE 13: BLOCK-WRITE-CYCLE STATE TABLE CYCLE Block-write operation (nonmasked) Block-write operation with nonpersistent write-per-bit Block-write operation with persistent write-per-bit 1 H L L STATE 2 3 Don't Care Valid Data Write Mask Valid Data Don't Care Valid Data SM55161A Production Write-mask data 0: I/O write disable 1: I/O write enable DQ Column-mask data DQi - DQi + 7 0: column-write disable (i = 0,8) 1: column-write enable COLUMN MASK DATA DQ0-15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 COLUMN MASK DATA Column 0 (A0 = 0, A1 = 0, A2 = 0) Column 1 (A0 = 1, A1 = 0, A2 = 0) Column 2 (A0 = 0, A1 = 1, A2 = 0) Column 3 (A0 = 1, A1 = 1, A2 = 0) Column 4 (A0 = 0, A1 = 0, A2 = 1) Column 5 (A0 = 1, A1 = 0, A2 = 1) Column 6 (A0 = 0, A1 = 1, A2 = 1) Column 7 (A0 = 1, A1 = 1, A2 = 1) Column 0 (A0 = 0, A1 = 0, A2 = 0) Column 1 (A0 = 1, A1 = 0, A2 = 0) Column 2 (A0 = 0, A1 = 1, A2 = 0) Column 3 (A0 = 1, A1 = 1, A2 = 0) Column 4 (A0 = 0, A1 = 0, A2 = 1) Column 5 (A0 = 1, A1 = 0, A2 = 1) Column 6 (A0 = 0, A1 = 1, A2 = 1) Column 7 (A0 = 1, A1 = 1, A2 = 1) Lower Byte Low: Mask High: No Mask Upper Byte Low: Mask High: No Mask SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 47 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 39: ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE TIMING SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 48 VRAM Austin Semiconductor, Inc. CYCLE Block-write operation (nonmasked) Block-write operation with nonpersistent write-per-bit Block-write operation with persistent write-per-bit 1 H L L STATE 2 3 Don't Care Valid Data Write Mask Valid Data Don't Care Valid Data SM55161A Production TABLE 14: ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE STATE TABLE Write-mask data 0: I/O write disable 1: I/O write enable DQ Column-mask data DQi - DQi + 7 0: column-write disable (i = 0,8) 1: column-write enable COLUMN MASK DATA DQ0-15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 COLUMN MASK DATA Column 0 (A0 = 0, A1 = 0, A2 = 0) Column 1 (A0 = 1, A1 = 0, A2 = 0) Column 2 (A0 = 0, A1 = 1, A2 = 0) Column 3 (A0 = 1, A1 = 1, A2 = 0) Column 4 (A0 = 0, A1 = 0, A2 = 1) Column 5 (A0 = 1, A1 = 0, A2 = 1) Column 6 (A0 = 0, A1 = 1, A2 = 1) Column 7 (A0 = 1, A1 = 1, A2 = 1) Column 0 (A0 = 0, A1 = 0, A2 = 0) Column 1 (A0 = 1, A1 = 0, A2 = 0) Column 2 (A0 = 0, A1 = 1, A2 = 0) Column 3 (A0 = 1, A1 = 1, A2 = 0) Column 4 (A0 = 0, A1 = 0, A2 = 1) Column 5 (A0 = 1, A1 = 0, A2 = 1) Column 6 (A0 = 0, A1 = 1, A2 = 1) Column 7 (A0 = 1, A1 = 1, A2 = 1) Lower Byte Low: Mask High: No Mask Upper Byte Low: Mask High: No Mask SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 49 VRAM Austin Semiconductor, Inc. FIGURE 40: RAS\-ONLY REFRESH-CYCLE TIMING SM55161A Production SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 50 VRAM Austin Semiconductor, Inc. FIGURE 41: CBR-REFRESH-CYCLE TIMING SM55161A Production TABLE 15: CBR-CYCLE STATE TABLE CYCLE CBR refresh with option reset CBR refresh with no reset CBR refresh with stop-point set and no reset 1 Don't Care Don't Care Stop Address STATE 2 L H H 3 H H L SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 51 VRAM Austin Semiconductor, Inc. FIGURE 42: HIDDEN-REFRESH-CYCLE TIMING SM55161A Production TABLE 16: HIDDEN-REFRESH-CYCLE STATE TABLE CYCLE CBR refresh with option reset CBR refresh with no reset CBR refresh with stop-point set and no reset 1 Don't Care Don't Care Stop Address STATE 2 L H H 3 H H L SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 52 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 43: FULL-REGISTER TRANSFER-READ TIMING, EARLY-LOAD OPERATIONS NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written to from the 512 corresponding columns of the selected row. B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be shifted out of the registers. Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive transition of SC. C. A0 - A8. D. Early-load operation is defined as th(TRG) MIN < th(TRG) < td(RLTH) MIN. E. There must be no rising transitions. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 53 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 44: FULL-REGISTER TRANSFER READ-TIMING, REAL-TIME LOAD OPERATION/LATE-LOAD OPERATION NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written to from the 512 corresponding columns of the selected row. B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be shifted out of the registers. Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive transition of SC. C. A0-A8. D. Late load operation is defined as td(THRH) < 0 ns. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 54 VRAM Austin Semiconductor, Inc. FIGURE 45: SPLIT-REGISTER-TRANSFER-READ TIMING SM55161A Production NOTES: A. A0-A7: tap point of the given half; A8: identifies the DRAM row half SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 55 VRAM Austin Semiconductor, Inc. FIGURE 46: SERIAL-READ-CYCLE TIMING (SE\ = VIL) SM55161A Production NOTES: A. While the data is being read through the serial-data register, TRG\ is a don't care; however, TRG\ must be held high when RAS\ goes low. This is to avoid the initiation of a register-data transfer operation. B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the read mode by performing a transfer-read cycle. FIGURE 47: SERIAL-WRITE-CYCLE TIMING SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 56 VRAM Austin Semiconductor, Inc. SM55161A Production FIGURE 48: SERIAL-READ TIMING (SE\-CONTROLLED READ) NOTES: A. While the data is being read through the serial-data register, TRG\ is a don't care; however, TRG\ must be held high when RAS\ goes low. This is to avoid the initiation of a register-data transfer operation. B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the read mode by performing a transfer-read cycle. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 57 VRAM Austin Semiconductor, Inc. FIGURE 49: SPLIT-REGISTER OPERATING SEQUENCE SM55161A Production NOTES: A. To achieve proper split-register operation, a full-register-transfer read must be performed before the first split-register-transfer cycle. This is necessary to initialize the data register and the starting tap location. First serial access can begin either after the full-register-transfer-read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after the first split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register transfer-read cycle and the first split-register cycle. B. A split-register transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the rising edge of the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\ of the split-register-transfer cycle into the inactive half. After the td(MSRL) requirement is met, the split-register transfer into the inactive half must also satisfy the minimum td(RHMS) requirement. td(RHMS) is the minimum delay time between the rising edge of RAS\ of the split-register-transfer cycle into the inactive half and the rising edge of the serial clock of the last bit (bit 255 or 511). SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 58 VRAM Austin Semiconductor, Inc. FIGURE 50: MASKED WRITE TRANSFER SM55161A Production NOTES: 1. SE\ = "L" 2. There must be no rising transitions. 3. QSF = "L" - Lower SAM (0-255) is active. QSF = "H" - Upper SAM (256-511) is active. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 59 VRAM Austin Semiconductor, Inc. FIGURE 51: MASKED SPLIT WRITE TRANSFER SM55161A Production NOTES: 1. SE\ = "L" 2. QSF = "L" - Lower SAM (0-255) is active. QSF = "H" - Upper SAM (256-511) is active. 3. Si is the SAM start address in before SWT. 4. STOP i and STOP j are programmable stop addresses. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 60 VRAM Austin Semiconductor, Inc. SM55161A Production MECHANICAL DEFINITIONS* Package Designator GB SMD 5962-94549, Case Outline X NOTES: 1. All linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. Index mark may appear on top or bottom depending on package vendor. 4. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within 0.015 (0,38) radius relative to the center of the ceramic. 5. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. 6. The pins can be gold plated or solder dipped. 7. Falls within MIL-STD-1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-066AA, respectively SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 61 VRAM Austin Semiconductor, Inc. SM55161A Production MECHANICAL DEFINITIONS* Package Designator HKC SMD 5962-94549, Case Outline Y NOTES: 1. 2. 3. 4. 5. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. All leads not shown for clarity purposes. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 62 VRAM Austin Semiconductor, Inc. SM55161A Production ORDERING INFORMATION EXAMPLE: SM55161A-75GBI Prefix* SM SMX SM SMX SM SMX Part Number 55161A 55161A 55161A 55161A 55161A 55161A Speed -70 -70 -75 -75 -80 -80 Package GB GB GB GB GB GB Temp M or I M or I M or I M or I M or I M or I EXAMPLE: SM55161A-80HKCM Prefix* SM SMX SM SMX SM SMX Part Number 55161A 55161A 55161A 55161A 55161A 55161A Speed -70 -70 -75 -75 -80 -80 Package HKC HKC HKC HKC HKC HKC Temp M or I M or I M or I M or I M or I M or I SM Prefix: Standard Military Processing using MIL-STD-883C flow & methods but non-complaint to para 1.2.1 SMX Prefix: strictly commercial flow samples I suffix: -40C to +85C M suffix: -55C to 125C SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 63 VRAM Austin Semiconductor, Inc. SM55161A Production ASI TO DSCC PART NUMBER CROSS REFERENCE Package Designator GB ASI Part # SMD Part # Package Designator HKC ASI Part # SMD Part # TO BE COMPLETED WHEN SMD LISTING IS RELEASED TO BE COMPLETED WHEN SMD LISTING IS RELEASED SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 64 |
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